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ds05-20914-2e fujitsu semiconductor data sheet flash memory cmos 128 m (16m 8/8m 16) bit mirrorflash tm * mbm29pl12lm 10 description the mbm29pl12lm is a 128m-bit, 3.0 v-only flash memory organized as 16m bytes by 8 bits or 8m words by 16 bits. the mbm29pl12lm is offered in 58-pin tsop (1) and 80-ball fbga. the device is designed to be programmed in-system with the standard 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. (continued) product line up note s : ? programming in byte mode ( 8 ) is prohibited. ? programming to the address that already contains data is prohibited . (it is mandatory to erase data prior to overprogram on the same address.) packages * : mirrorflash tm is a trademark of fujitsu limited. part no. mbm29pl12lm 10 v cc 3.0 v to 3.6 v max address access time 100 ns max ce access time 100 ns max page read access time 30 ns 56-pin plastic tsop (1) 80-ball plastic fbga (fpt-56p-m01) (bga-80p-m02)
mbm29pl12lm 10 2 (continued) the standard mbm29pl12lm offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29pl12lm supports command set compatible with jedec single-power-supply eeproms standard. commands are written into the command register. the register contents serve as input to an internal state- machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29pl12lm is programmed by executing the program command sequence. this will invoke the em- bedded program algorithm tm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm tm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. all sectors are erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 . once the end of a program or erase cycle has been completed, the devices internally return to the read mode. fujitsu flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the devices electrically erase all bits within a sector simulta- neously via hot-hole assisted erase. the words are programmed one word at a time using the eprom program- ming mechanism of hot electron injection.
mbm29pl12lm 10 3 features ? 0.23 m process technology single 3.0 v read, program and erase minimizes system level power requirements industry-standard pinouts 56-pin tsop (1) 80-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles high performance page mode fast 8 bytes / 4 words access capabililty sector erase architecture 256 64k byte and 32k word sectors any combination of sectors can be concurrently erased. also supports full chip erase hiddenrom 256 bytes / 128 words of hiddenrom, accessible through a ?hiddenrom entry? command sequence factory serialized and protected to provide a secure electronic serial number (esn) wp /acc input pin at v il , allows protection of outermost two 8k bytes / 4k words sectors, regardless of sector protection/unpro- tection status at v acc , increases program performance embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device low v cc write inhibit 2.5 v sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector protect command ? fast programming function by extended command temporary sector group unprotection temporary sector group unprotection via the reset pin this feature allows code changes in previously locked sectors ? in accordance with cfi (c ommon f lash memory i nterface) * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29pl12lm 10 4 pin assignments n.c. a 22 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we reset a 21 wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 (top view) n.c. n.c. a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 n.c. v ccq (marking side) 56-pin tsop (1) fpt-56p-m01 e6 a 10 e5 e4 a 18 e3 a 6 e2 a 2 g4 dq 2 g3 dq 0 g2 a 0 h6 dq 14 h5 dq 12 h4 dq 10 h3 dq 8 h2 ce f6 a 11 f3 a 5 f2 a 1 j6 dq 13 j5 v cc j4 dq 11 j3 dq 9 j2 oe k6 dq 6 k5 dq 4 k4 dq 3 k3 dq 1 k2 v ss l7 n.c. l2 n.c. l1 n.c. l8 n.c. d6 a 8 d5 reset d4 wp/acc d3 a 17 d2 a 4 m7 n.c. m2 n.c. m1 n.c. m8 n.c. c6 a 9 c5 we c4 ry/by c3 a 7 c2 a 3 b7 n.c. b1 n.c. b8 n.c. a7 n.c. a2 n.c. a1 n.c. a8 n.c. f5 a 19 g5 dq 5 f4 a 20 g6 dq 7 * * * * ** * * * * * * * * * e7 a 14 g7 a 16 h7 byte f7 a 15 j7 dq 15 /a -1 k7 v ss d7 a 12 c7 a 13 e8 g8 h8 f8 j8 k8 v ss d8 c8 n.c. * v ccq n.c. * e1 g1 h1 f1 j1 k1 v cc d1 c1 n.c. * v ccq n.c. * n.c. * n.c. * n.c. * v ss b2 a 22 n.c. * n.c. * n.c. * n.c. * a 21 80-ball fbga bga-80p-m02
mbm29pl12lm 10 5 pin descriptions mbm29pl12lm pin configuration pin function a 22 to a 0 , a -1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable wp /acc hardware write protection/program acceleration reset hardware reset pin/temporary sector group unprotection byte select 8-bit or 16-bit mode ry/by ready/busy output v cc device power supply v ccq output voltage v ss device ground n.c. no internal connection
mbm29pl12lm 10 6 block diagram logic symbol v ss v cc we ce a 1 , a 0 oe erase voltage generator dq 15 to dq 0 state control command register program voltage generator address latch x decoder y decoder cell matrix y gating chip enable output enable logic data latch stb stb reset wp / acc timer for program / erase v ccq input / output buffers a 22 to a 2 byte (a 1 , ) 23 a 22 to a 0 we oe ce dq 15 to dq 0 wp/acc reset 16 or 8 byte ry/by a -1 v ccq
mbm29pl12lm 10 7 device bus operation mbm29pl12lm user bus operations (word mode : byte = v ih ) legend : l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. hi-z = high-z, v id = 11.5 to 12.5v *1 : manufacturer and device codes may also be accessed via a command register write sequence. see ?mbm29pl12lm standard command definitions?. *2 : refer to sector group protection. *3 : protects the first 32k words sector (sa0) *4 : d in or d out as required by command sequence, data polling, or sector protect algorithm *5 : if wp /acc = v il , the first sector remain protected. if wp /acc = v ih , the first sector will be protected or unprotected as determined by the method specified in "sector group protection". operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 0 to dq 15 reset wp / acc standby hxxxxxxxx hi-z h x autoselect manufacture code* 1 llhlllllv id code h x autoselect device code* 1 llhhllllv id code h x read l l h a 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable lhhxxxxxx hi-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 *4 h *5 enable sector group protection* 2 lhllhlllx *4 v id h temporary sector group unprotection xxxxxxxxx *4 v id h reset (hardware) xxxxxxxxx hi-z l x sector write protection* 3 xxxxxxxxx x h l
mbm29pl12lm 10 8 mbm29pl12lm user bus operations (byte mode : byte = v il ) legend : l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. hi-z = high-z, v id = 11.5 to 12.5v *1 : manufacturer and device codes may also be accessed via a command register write sequence. see ?mbm29pl12lm standard command definitions?. *2 : refer to sector group protection. *3 : protects the first 64k bytes sectors *4 : d in or d out as required by command sequence, data polling, or sector protect algorithm *5 : if wp /acc = v il , the first sector remain protected. if wp /acc = v ih , the first sector will be protected or unprotected as determined by the method specified in "sector group protection". operation ce oe we dq 15 / a -1 a 0 a 1 a 2 a 3 a 6 a 9 dq 0 to dq 7 reset wp / acc standby h x x x x x x x x x hi-z h x autoselect manufacture code* 1 llh l lllllv id code h x autoselect device code* 1 l lh l hllllv id code h x read l l h a -1 a 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable l h h x x x x x x x hi-z h x write (erase) l h l a -1 a 0 a 1 a 2 a 3 a 6 a 9 *4 h *5 enable sector group protection* 2 lhlllhlllx*4 v id h temporary sector group unprotection xxx x xxxxxx *4 v id h reset (hardware) x x x x x x x x x x hi-z l x sector write protection* 3 xxx x xxxxxx x h l
mbm29pl12lm 10 9 mbm29pl12lm standard command definitions* 1 (continued) command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset* 2 word/ byte 1 xxxh f0h ? ? ? ? ? ? ? ? ? ? reset* 2 word 3 555h aah 2aah 55h 555h f0h ra * 13 rd * 13 ???? byte aaah 555h aaah autoselect (device id) word 3 555h aah 2aah 55h 555h 90h 00h * 13 04h* 13 ???? byte aaah 555h aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h program/erase suspend* 3 1 xxxh b0h ? ? ? ? ? ? ? ? ? ? program/erase resume* 3 1 xxxh 30h ? ? ? ? ? ? ? ? ? ? set to fast mode* 4 word 3 555h aah 2aah 55h 555h 20h ? ? ? ? ? ? byte aaah 555h aaah fast program* 4 word 2 xxxh a0h pa pd ? ? ? ? ? ? ? ? reset from fast mode* 5 word/ byte 2 xxxh 90h xxxh 00h * 12 ?? ? ? ???? write to buffer word 20 555h aah 2aah 55h sa 25h sa 0fh pa pd wbl pd byte aaah 555h program buffer to flash (confirm) 1 sa 29h ? ? ? ? ? ? ? ? ? ? write to buffer abort reset* 6 word 3 555h aah 2aah 55h 555h f0h ? ? ? ? ? ? byte aaah 555h aaah extended sector group protection * 7, * 8 word 4 xxxh 60h sga 60h sga 40h sga * 13 sd * 13 ???? byte query* 9 word 1 55h 98h ? ? ? ? ? ? ? ? ? ? byte aah hiddenrom entry* 10 word 3 555h aah 2aah 55h 555h 88h ? ? ? ? ? ? byte aaah 555h aaah hiddenrom program * 10, * 11 word 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? byte aaah 555h aaah hiddenrom exit* 11 word 4 555h aah 2aah 55h 555h 90h xxxh 00h ? ? ? ? byte aaah 555h aaah
mbm29pl12lm 10 10 (continued) legend : address bits a 22 to a 15 = x = ?h? or ?l? for all address commands except for program address (pa), sector address (sa) and sector group address (sga). bus operations are defined in ?mbm29pl12lm user bus operations (word mode : byte = v ih )? and ?mbm29pl12lm user bus operations (byte mode : byte = v il )?. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be programmed / erased. the combination of a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , and a 15 will uniquely select any sector. see ?sector address table (mbm29pl12lm)?. sga = sector group address to be protected. see ?sector group address table (mbm29pl12lm)?. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write plus. wbl = write buffer location hra = address of the hiddenrom area ; word mode : 000000h to 000007h byte mode : 000000h to 0000ffh *1 : the command combinations not described in ?mbm29pl12lm standard command definitions? are illegal. *2 : both of these reset commands are equivalent except for "write to buffer abort reset". *3 : the erase suspend and erase resume command are valid only during a sector erase operation. *4 : the set to fast mode command is required prior to the fast program command. *5 : the reset from fast mode command is required to return to the read mode when the device is in fast mode. *6 : reset to the read mode. the write to buffer abort reset command is required after the write to buffer operation was aborted. *7 : this command is valid while reset = v id . *8 : sector group address (sga) with a 6 = 0, a 3 = 0, a 2 = 0, a 1 = 1, and a 0 = 0 *9 : the valid address are a 6 to a 0 . *10 : the hiddenrom entry command is required prior to the hiddenrom programming. *11 : this command is valid during hiddenrom mode. *12 : the data ?f0h? is also acceptable. *13 : indicates read cycle.
mbm29pl12lm 10 11 sector group protection verify autoselect codes *1 : a -1 is for byte mode. *2 : at word mode, a read cycle at address 01h ( at byte mode, 02h ) outputs device code. when 227eh ( at byte mode, 7eh ) is output, it indicates that reading two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of 0eh ( at byte mode, 1ch ), as well as at 0fh ( at byte mode, 1eh ). *3 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *4 : at ce = fix, designate sga as ( a6, a3, a2, a1, a0 ) = ( 0, 0, 0, 1, 0 ) , with an interval of one cycle after we rising ( the last write command ) . type a 22 to a 15 a 6 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufacturer?s code x v il v il v il v il v il v il 04h device code word xv il v il v il v il v ih x 227eh byte v il 7eh extended device code* 2 word xv il v ih v ih v ih v il x 2212h byte v il 12h word xv il v ih v ih v ih v ih x 2200h byte v il 00h sector group protection* 4 sector group addresses v il v il v il v ih v il v il *3
mbm29pl12lm 10 12 sector address table (mbm29pl12lm) (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa0 00000000 64/32 00 0000h to 00ffffh 000000h to 007fffh sa1 00000001 64/32 01 0000h to 01ffffh 008000h to 00ffffh sa2 00000010 64/32 02 0000h to 02ffffh 010000h to 017fffh sa3 00000011 64/32 03 0000h to 03ffffh 018000h to 01ffffh sa4 00000100 64/32 04 0000h to 04ffffh 020000h to 027fffh sa5 00000101 64/32 05 0000h to 05ffffh 028000h to 02ffffh sa6 00000110 64/32 06 0000h to 06ffffh 030000h to 037fffh sa7 00000111 64/32 07 0000h to 07ffffh 038000h to 03ffffh sa8 00001000 64/32 08 0000h to 08ffffh 040000h to 047fffh sa9 00001001 64/32 09 0000h to 09ffffh 048000h to 04ffffh sa10 00001010 64/32 0a 0000h to 0affffh 050000h to 057fffh sa11 00001011 64/32 0b 0000h to 0bffffh 058000h to 05ffffh sa12 00001100 64/32 0c 0000h to 0cffffh 060000h to 067fffh sa13 00001101 64/32 0d 0000h to 0dffffh 068000h to 06ffffh sa14 00001110 64/32 0e 0000h to 0effffh 070000h to 077fffh sa15 00001111 64/32 0f 0000h to 0fffffh 078000h to 07ffffh sa16 00010000 64/32 10 0000h to 10ffffh 080000h to 087fffh sa17 00010001 64/32 11 0000h to 11ffffh 088000h to 08ffffh sa18 00010010 64/32 12 0000h to 12ffffh 090000h to 097fffh sa19 00010011 64/32 13 0000h to 13ffffh 098000h to 09ffffh sa20 00010100 64/32 14 0000h to 14ffffh 0a0000h to 0a7fffh sa21 00010101 64/32 15 0000h to 15ffffh 0a8000h to 0affffh sa22 00010110 64/32 16 0000h to 16ffffh 0b0000h to 0b7fffh sa23 00010111 64/32 17 0000h to 17ffffh 0b8000h to 0bffffh sa24 00011000 64/32 18 0000h to 18ffffh 0c0000h to 0c7fffh sa25 00011001 64/32 19 0000h to 19ffffh 0c8000h to 0cffffh sa26 00011010 64/32 1a 0000h to 1affffh 0d0000h to 0d7fffh sa27 00011011 64/32 1b 0000h to 1bffffh 0d8000h to 0dffffh sa28 00011100 64/32 1c 0000h to 1cffffh 0e0000h to 0e7fffh sa29 00011101 64/32 1d 0000h to 1dffffh 0e8000h to 0effffh sa30 00011110 64/32 1e 0000h to 1effffh 0f0000h to 0f7fffh
mbm29pl12lm 10 13 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa31 00011111 64/32 1f0000h to 1 fffffh 0f8000h to 0fffffh sa32 00100000 64/32 200000h to 20f fffh 100000h to 107fffh sa33 00100001 64/32 210000h to 21f fffh 108000h to 10ffffh sa34 00100010 64/32 220000h to 22f fffh 110000h to 117fffh sa35 00100011 64/32 230000h to 23f fffh 118000h to 11ffffh sa36 00100100 64/32 240000h to 24f fffh 120000h to 127fffh sa37 00100101 64/32 250000h to 25f fffh 128000h to 12ffffh sa38 00100110 64/32 260000h to 26f fffh 130000h to 137fffh sa39 00100111 64/32 270000h to 27f fffh 138000h to 13ffffh sa40 00101000 64/32 280000h to 28f fffh 140000h to 147fffh sa41 00101001 64/32 290000h to 29f fffh 148000h to 14ffffh sa42 00101010 64/32 2a0000h to 2affffh150000h to 157fffh sa43 00101011 64/32 2b0000h to 2bffffh158000h to 15 ffffh sa44 00101100 64/32 2c0000h to 2c ffffh 160000h to 167fffh sa45 00101101 64/32 2d0000h to 2d ffffh 168000h to 16ffffh sa46 00101110 64/32 2e0000h to 2effffh170000h to 177fffh sa47 00101111 64/32 2f0000h to 2 fffffh 178000h to 17ffffh sa48 00110000 64/32 300000h to 30f fffh 180000h to 187fffh sa49 00110001 64/32 310000h to 31f fffh 188000h to 18ffffh sa50 00110010 64/32 320000h to 32f fffh 190000h to 197fffh sa51 00110011 64/32 330000h to 33f fffh 198000h to 19ffffh sa52 00110100 64/32 340000h to 34f fffh 1a0000h to 1a7fffh sa53 00110101 64/32 350000h to 35f fffh 1a8000h to 1affffh sa54 00110110 64/32 360000h to 36f fffh 1b0000h to 1b7fffh sa55 00110111 64/32 370000h to 37f fffh 1b8000h to 1bffffh sa56 00111000 64/32 380000h to 38f fffh 1c0000h to 1c7fffh sa57 00111001 64/32 390000h to 39f fffh 1c8000h to 1cffffh sa58 00111010 64/32 3a0000h to 3affffh1d0000h to 1d7 fffh sa59 00111011 64/32 3b0000h to 3bffffh1d8000h to 1d ffffh sa60 00111100 64/32 3c0000h to 3c ffffh 1e0000h to 1e7fffh sa61 00111101 64/32 3d0000h to 3d ffffh 1e8000h to 1effffh sa62 00111110 64/32 3e0000h to 3effffh1f0000h to 1f7 fffh
mbm29pl12lm 10 14 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa63 0011111 1 64/32 3f0000h to 3 fffffh 1f8000h to 1fffffh sa64 0100000 0 64/32 400000h to 40f fffh 200000h to 207fffh sa65 0100000 1 64/32 410000h to 41f fffh 208000h to 20ffffh sa66 0100001 0 64/32 420000h to 42f fffh 210000h to 217fffh sa67 0100001 1 64/32 430000h to 43f fffh 218000h to 21ffffh sa68 0100010 0 64/32 440000h to 44f fffh 220000h to 227fffh sa69 0100010 1 64/32 450000h to 45f fffh 228000h to 22ffffh sa70 0100011 0 64/32 460000h to 46f fffh 230000h to 237fffh sa71 0100011 1 64/32 470000h to 47f fffh 238000h to 23ffffh sa72 0100100 0 64/32 480000h to 48f fffh 240000h to 247fffh sa73 0100100 1 64/32 490000h to 49f fffh 248000h to 24ffffh sa74 0100101 0 64/32 4a0000h to 4affffh250000h to 257fffh sa75 0100101 1 64/32 4b0000h to 4bffffh258000h to 25 ffffh sa76 0100110 0 64/32 4c0000h to 4c ffffh 260000h to 267fffh sa77 0100110 1 64/32 4d0000h to 4d ffffh 268000h to 26ffffh sa78 0100111 0 64/32 4e0000h to 4effffh270000h to 277fffh sa79 0100111 1 64/32 4f0000h to 4 fffffh 278000h to 27ffffh sa80 0101000 0 64/32 500000h to 50f fffh 280000h to 287fffh sa81 0101000 1 64/32 510000h to 51f fffh 288000h to 28ffffh sa82 0101001 0 64/32 520000h to 52f fffh 290000h to 297fffh sa83 0101001 1 64/32 530000h to 53f fffh 298000h to 29ffffh sa84 0101010 0 64/32 540000h to 54f fffh 2a0000h to 2a7fffh sa85 0101010 1 64/32 550000h to 55f fffh 2a8000h to 2affffh sa86 0101011 0 64/32 560000h to 56f fffh 2b0000h to 2b7fffh sa87 0101011 1 64/32 570000h to 57f fffh 2b8000h to 2bffffh sa88 0101100 0 64/32 580000h to 58f fffh 2c0000h to 2c7fffh sa89 0101100 1 64/32 590000h to 59f fffh 2c8000h to 2cffffh sa90 0101101 0 64/32 5a0000h to 5affffh2d0000h to 2d7 fffh sa91 0101101 1 64/32 5b0000h to 5bffffh2d8000h to 2d ffffh sa92 0101110 0 64/32 5c0000h to 5c ffffh 2e0000h to 2ee7ffh sa93 0101110 1 64/32 5d0000h to 5d ffffh 2e8000h to 2effffh sa94 0101111 0 64/32 5e0000h to 5effffh2f0000h to 2f7 fffh
mbm29pl12lm 10 15 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa95 01011111 64/32 5f0000h to 5 fffffh 2f8000h to 2fffffh sa96 01100000 64/32 600000h to 60f fffh 300000h to 307fffh sa97 01100001 64/32 610000h to 61f fffh 308000h to 30ffffh sa98 01100010 64/32 620000h to 62f fffh 310000h to 317fffh sa99 01100011 64/32 630000h to 63f fffh 318000h to 31ffffh sa10001100100 64/32 640000h to 64f fffh 320000h to 327fffh sa10101100101 64/32 650000h to 65f fffh 328000h to 32ffffh sa10201100110 64/32 660000h to 66f fffh 330000h to 337fffh sa10301100111 64/32 670000h to 67f fffh 338000h to 33ffffh sa10401101000 64/32 680000h to 68f fffh 340000h to 347fffh sa10501101001 64/32 690000h to 69f fffh 348000h to 34ffffh sa10601101010 64/32 6a0000h to 6affffh350000h to 357fffh sa10701101011 64/32 6b0000h to 6bffffh358000h to 35 ffffh sa10801101100 64/32 6c0000h to 6c ffffh 360000h to 367fffh sa10901101101 64/32 6d0000h to 6d ffffh 368000h to 36ffffh sa11001101110 64/32 6e0000h to 6effffh370000h to 377fffh sa11101101111 64/32 6f0000h to 6 fffffh 378000h to 37ffffh sa11201110000 64/32 700000h to 70f fffh 380000h to 387fffh sa11301110001 64/32 710000h to 71f fffh 388000h to 38ffffh sa11401110010 64/32 720000h to 72f fffh 390000h to 397fffh sa11501110011 64/32 730000h to 73f fffh 398000h to 39ffffh sa11601110100 64/32 740000h to 74f fffh 3a0000h to 3a7fffh sa11701110101 64/32 750000h to 75f fffh 3a8000h to 3affffh sa11801110110 64/32 760000h to 76f fffh 3b0000h to 3b7fffh sa11901110111 64/32 770000h to 77f fffh 3b8000h to 3bffffh sa12001111000 64/32 780000h to 78f fffh 3c0000h to 3c7fffh sa12101111001 64/32 790000h to 79f fffh 3c8000h to 3cffffh sa12201111010 64/32 7a0000h to 7affffh3d0000h to 3d7 fffh sa12301111011 64/32 7b0000h to 7bffffh3d8000h to 3d ffffh sa12401111100 64/32 7c0000h to 7c ffffh 3e0000h to 3e7fffh
mbm29pl12lm 10 16 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa12501111101 64/32 7d0000h to 7d ffffh 3e8000h to 3effffh sa12601111110 64/32 7e0000h to 7effffh3f0000h to 3f7 fffh sa12701111111 64/32 7f0000h to 7 fffffh 3f8000h to 3fffffh sa12810000000 64/32 800000h to 80f fffh 400000h to 407fffh sa12910000001 64/32 810000h to 81f fffh 408000h to 40ffffh sa13010000010 64/32 820000h to 82f fffh 410000h to 417fffh sa13110000011 64/32 830000h to 83f fffh 418000h to 41ffffh sa13210000100 64/32 840000h to 84f fffh 420000h to 427fffh sa13310000101 64/32 850000h to 85f fffh 428000h to 42ffffh sa13410000110 64/32 860000h to 86f fffh 430000h to 437fffh sa13510000111 64/32 870000h to 87f fffh 438000h to 43ffffh sa13610001000 64/32 880000h to 88f fffh 440000h to 447fffh sa13710001001 64/32 890000h to 89f fffh 448000h to 44ffffh sa13810001010 64/32 8a0000h to 8affffh450000h to 457fffh sa13910001011 64/32 8b0000h to 8bffffh458000h to 45 ffffh sa14010001100 64/32 8c0000h to 8c ffffh 460000h to 467fffh sa14110001101 64/32 8d0000h to 8d ffffh 468000h to 46ffffh sa14210001110 64/32 8e0000h to 8effffh470000h to 477fffh sa14310001111 64/32 8f0000h to 8 fffffh 478000h to 47ffffh sa14410010000 64/32 900000h to 90f fffh 480000h to 487fffh sa14510010001 64/32 910000h to 91f fffh 488000h to 48ffffh sa14610010010 64/32 920000h to 92f fffh 490000h to 497fffh sa14710010011 64/32 930000h to 93f fffh 498000h to 49ffffh sa14810010100 64/32 940000h to 94f fffh 4a0000h to 4a7fffh sa14910010101 64/32 950000h to 95f fffh 4a8000h to 4affffh sa15010010110 64/32 960000h to 96f fffh 4b0000h to 4b7fffh sa15110010111 64/32 970000h to 97f fffh 4b8000h to 4bffffh sa15210011000 64/32 980000h to 98f fffh 4c0000h to 4c7fffh sa15310011001 64/32 990000h to 99f fffh 4c8000h to 4cffffh sa15410011010 64/32 9a0000h to 9affffh4d0000h to 4d7 fffh sa15510011011 64/32 9b0000h to 9bffffh4d8000h to 4d ffffh
mbm29pl12lm 10 17 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa15610011100 64/32 9c0000h to 9c ffffh 4e0000h to 4e7fffh sa15710011101 64/32 9d0000h to 9d ffffh 4e8000h to 4effffh sa15810011110 64/32 9e0000h to 9effffh4f0000h to 4f7 fffh sa15910011111 64/32 9f0000h to 9 fffffh 4f8000h to 4fffffh sa16010100000 64/32 a00000h to a0ffffh500000h to 507fffh sa16110100001 64/32 a10000h to a1ffffh508000h to 50 ffffh sa16210100010 64/32 a20000h to a2ffffh510000h to 517fffh sa16310100011 64/32 a30000h to a3ffffh518000h to 51 ffffh sa16410100100 64/32 a40000h to a4ffffh520000h to 527fffh sa16510100101 64/32 a50000h to a5ffffh528000h to 52 ffffh sa16610100110 64/32 a60000h to a6ffffh530000h to 537fffh sa16710100111 64/32 a70000h to a7ffffh538000h to 53 ffffh sa16810101000 64/32 a80000h to a8ffffh540000h to 547fffh sa16910101001 64/32 a90000h to a9ffffh548000h to 54 ffffh sa17010101010 64/32 aa0000h to aa ffffh 550000h to 557fffh sa17110101011 64/32 ab0000h to ab ffffh 558000h to 55ffffh sa17210101100 64/32 ac0000h to acffffh560000h to 567fffh sa17310101101 64/32 ad0000h to adffffh568000h to 56 ffffh sa17410101110 64/32 ae0000h to ae ffffh 570000h to 577fffh sa17510101111 64/32 af0000h to a fffffh 578000h to 57ffffh sa17610110000 64/32 b00000h to b0ffffh580000h to 587fffh sa17710110001 64/32 b10000h to b1ffffh588000h to 58 ffffh sa17810110010 64/32 b20000h to b2ffffh590000h to 597fffh sa17910110011 64/32 b30000h to b3ffffh598000h to 59 ffffh sa18010110100 64/32 b40000h to b4ffffh5a0000h to 5a7 fffh sa18110110101 64/32 b50000h to b5ffffh5a8000h to 5a ffffh sa18210110110 64/32 b60000h to b6ffffh5b0000h to 5b7 fffh sa18310110111 64/32 b70000h to b7ffffh5b8000h to 5b ffffh sa18410111000 64/32 b80000h to b8ffffh5c0000h to 5c7 fffh sa18510111001 64/32 b90000h to b9ffffh5c8000h to 5c ffffh
mbm29pl12lm 10 18 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa18610111010 64/32 ba0000h to ba ffffh 5d0000h to 5d7fffh sa18710111011 64/32 bb0000h to bb ffffh 5d8000h to 5dffffh sa18810111100 64/32 bc0000h to bcffffh5e0000h to 5e7 fffh sa18910111101 64/32 bd0000h to bdffffh5e8000h to 5e ffffh sa19010111110 64/32 be0000h to be ffffh 5f0000h to 5f7fffh sa19110111111 64/32 bf0000h to b fffffh 5f8000h to 5fffffh sa19211000000 64/32 c00000h to c0 ffffh 600000h to 607fffh sa19311000001 64/32 c10000h to c1 ffffh 608000h to 60ffffh sa19411000010 64/32 c20000h to c2 ffffh 610000h to 617fffh sa19511000011 64/32 c30000h to c3 ffffh 618000h to 61ffffh sa19611000100 64/32 c40000h to c4 ffffh 620000h to 627fffh sa19711000101 64/32 c50000h to c5 ffffh 628000h to 62ffffh sa19811000110 64/32 c60000h to c6 ffffh 630000h to 637fffh sa19911000111 64/32 c70000h to c7 ffffh 638000h to 63ffffh sa20011001000 64/32 c80000h to c8 ffffh 640000h to 647fffh sa20111001001 64/32 c90000h to c9 ffffh 648000h to 64ffffh sa20211001010 64/32 ca0000h to caffffh650000h to 657fffh sa20311001011 64/32 cb0000h to cbffffh658000h to 65 ffffh sa20411001100 64/32 cc0000h to cc ffffh 660000h to 667fffh sa20511001101 64/32 cd0000h to cd ffffh 668000h to 66ffffh sa20611001110 64/32 ce0000h to ceffffh670000h to 677fffh sa20711001111 64/32 cf0000h to c fffffh 678000h to 67ffffh sa20811010000 64/32 d00000h to d0 ffffh 680000h to 687fffh sa20911010001 64/32 d10000h to d1 ffffh 688000h to 68ffffh sa21011010010 64/32 d20000h to d2 ffffh 690000h to 697fffh sa21111010011 64/32 d30000h to d3 ffffh 698000h to 69ffffh sa21211010100 64/32 d40000h to d4 ffffh 6a0000h to 6a7fffh sa21311010101 64/32 d50000h to d5 ffffh 6a8000h to 6affffh sa21411010110 64/32 d60000h to d6 ffffh 6b0000h to 6b7fffh sa21511010111 64/32 d70000h to d7 ffffh 6b8000h to 6bffffh
mbm29pl12lm 10 19 (continued) sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa21611011000 64/32 d80000h to d8 ffffh 6c0000h to 6c7fffh sa21711011001 64/32 d90000h to d9 ffffh 6c8000h to 6cffffh sa21811011010 64/32 da0000h to daffffh6d0000h to 6d7 fffh sa21911011011 64/32 db0000h to dbffffh6d8000h to 6d ffffh sa22011011100 64/32 dc0000h to dc ffffh 6e0000h to 6e7fffh sa22111011101 64/32 dd0000h to dd ffffh 6e8000h to 6effffh sa22211011110 64/32 de0000h to deffffh6f0000h to 6f7 fffh sa22311011111 64/32 df0000h to d fffffh 6f8000h to 6fffffh sa22411100000 64/32 e00000h to e0ffffh700000h to 707fffh sa22511100001 64/32 e10000h to e1ffffh708000h to 70 ffffh sa22611100010 64/32 e20000h to e2ffffh710000h to 717fffh sa22711100011 64/32 e30000h to e3ffffh718000h to 71 ffffh sa22811100100 64/32 e40000h to e4ffffh720000h to 727fffh sa22911100101 64/32 e50000h to e5ffffh728000h to 72 ffffh sa23011100110 64/32 e60000h to e6ffffh730000h to 737fffh sa23111100111 64/32 e70000h to e7ffffh738000h to 73 ffffh sa23211101000 64/32 e80000h to e8ffffh740000h to 747fffh sa23311101001 64/32 e90000h to e9ffffh748000h to 74 ffffh sa23411101010 64/32 ea0000h to ea ffffh 750000h to 757fffh sa23511101011 64/32 eb0000h to eb ffffh 758000h to 75ffffh sa23611101100 64/32 ec0000h to ecffffh760000h to 767fffh sa23711101101 64/32 ed0000h to edffffh768000h to 76 ffffh sa23811101110 64/32 ee0000h to ee ffffh 770000h to 777fffh sa23911101111 64/32 ef0000h to e fffffh 778000h to 77ffffh sa24011110000 64/32 f00000h to f0 ffffh 780000h to 787fffh sa24111110001 64/32 f10000h to f1 ffffh 788000h to 78ffffh sa24211110010 64/32 f20000h to f2 ffffh 790000h to 797fffh sa24311110011 64/32 f30000h to f3 ffffh 798000h to 79ffffh sa24411110100 64/32 f40000h to f4 ffffh 7a0000h to 7a7fffh sa24511110101 64/32 f50000h to f5 ffffh 7a8000h to 7affffh
mbm29pl12lm 10 20 (continued) note : the address range is a 22 to a -1 if in byte mode (byte = v il ) . the address range is a 22 to a 0 if in word mode (byte = v ih ) . sector a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size (kbytes/ kwords) ( 8) address range ( 16) address range sa246 11110110 64/32 f6 0000h to f6ffffh 7b0000h to 7b7fffh sa247 11110111 64/32 f7 0000h to f7ffffh 7b8000h to 7bffffh sa248 11111000 64/32 f8 0000h to f8ffffh 7c0000h to 7c7fffh sa249 11111001 64/32 f9 0000h to f9ffffh 7c8000h to 7cffffh sa250 11111010 64/32 fa 0000h to faffffh 7d0000h to 7d7fffh sa251 11111011 64/32 fb 0000h to fbffffh 7d8000h to 7dffffh sa252 11111100 64/32 fc 0000h to fcffffh 7e0000h to 7e7fffh sa253 11111101 64/32 fd 0000h to fdffffh 7e8000h to 7effffh sa254 11111110 64/32 fe 0000h to feffffh 7f0000h to 7f7fffh sa255 11111111 64/32 ff 0000h to ffffffh 7f8000h to 7fffffh
mbm29pl12lm 10 21 sector group address table (mbm29pl12lm) (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector group size (kbytes/kwords) sectors sga0 00000000 64/32 sa0 sga1 00000001 64/32 sa1 sga2 00000010 64/32 sa2 sga3 00000011 64/32 sa3 sga4 00000100 256/128 sa4 to sa7 sga5 00001000 256/128 sa8 to sa11 sga6 00001100 256/128 sa12 to sa15 sga7 00010000 256/128 sa16 to sa19 sga8 00010100 256/128 sa20 to sa23 sga9 00011000 256/128 sa24 to sa27 sga10 00011100 256/128 sa28 to sa31 sga11 00100000 256/128 sa32 to sa35 sga12 00100100 256/128 sa36 to sa39 sga13 00101000 256/128 sa40 to sa43 sga14 00101100 256/128 sa44 to sa47 sga15 00110000 256/128 sa48 to sa51 sga16 00110100 256/128 sa52 to sa55 sga17 00111000 256/128 sa56 to sa59 sga18 00111100 256/128 sa60 to sa63 sga19 01000000 256/128 sa64 to sa67 sga20 01000100 256/128 sa68 to sa71 sga21 01001000 256/128 sa72 to sa75 sga22 01001100 256/128 sa76 to sa79 sga23 01010000 256/128 sa80 to sa83 sga24 01010100 256/128 sa84 to sa87 sga25 01011000 256/128 sa88 to sa91 sga26 01011100 256/128 sa92 to sa95 sga27 01100000 256/128 sa96 to sa99 sga28 01100100 256/128 sa100 to sa103 sga29 01101000 256/128 sa104 to sa107 sga30 01101100 256/128 sa108 to sa111 sga31 01110000 256/128 sa112 to sa115 sga32 01110100 256/128 sa116 to sa119 sga33 01111000 256/128 sa120 to sa123 sga34 01111100 256/128 sa124 to sa127
mbm29pl12lm 10 22 (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector group size (kbytes/kwords) sectors sga35 10000000 256/128 sa128 to sa131 sga36 10000100 256/128 sa132 to sa135 sga37 10001000 256/128 sa136 to sa139 sga38 10001100 256/128 sa140 to sa143 sga39 10010000 256/128 sa144 to sa147 sga40 10010100 256/128 sa148 to sa151 sga41 10011000 256/128 sa152 to sa155 sga42 10011100 256/128 sa156 to sa159 sga43 10100000 256/128 sa160 to sa163 sga44 10100100 256/128 sa164 to sa167 sga45 10101000 256/128 sa168 to sa171 sga46 10101100 256/128 sa172 to sa175 sga47 10110000 256/128 sa176 to sa179 sga48 10110100 256/128 sa180 to sa183 sga49 10111000 256/128 sa184 to sa187 sga50 10111100 256/128 sa188 to sa191 sga51 11000000 256/128 sa192 to sa195 sga52 11000100 256/128 sa196 to sa199 sga53 11001000 256/128 sa200 to sa203 sga54 11001100 256/128 sa204 to sa207 sga55 11010000 256/128 sa208 to sa211 sga56 11010100 256/128 sa212 to sa215 sga57 11011000 256/128 sa216 to sa219 sga58 11011100 256/128 sa220 to sa223 sga59 11100000 256/128 sa224 to sa227 sga60 11100100 256/128 sa228 to sa231 sga61 11101000 256/128 sa232 to sa235 sga62 11101100 256/128 sa236 to sa239 sga63 11110000 256/128 sa240 to sa243 sga64 11110100 256/128 sa244 to sa247 sga65 11111000 256/128 sa248 to sa251 sga66 11111100 64/32 sa252 sga67 11111101 64/32 sa253 sga68 11111110 64/32 sa254 sga69 11111111 64/32 sa255
mbm29pl12lm 10 23 common flash memory interface code (continued) a 0 to a 6 dq 0 to dq 15 description 10h 11h 12h 0051h 0052h 0059h query-unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set (02h = fujitsu standard) 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = not applicable) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = not applicable) 1bh 0027h v cc min (write/erase) dq 7 to dq 4 : 1v/bit, dq 3 to dq 0 : 100 mv/bit 1ch 0036h v cc max (write/erase) dq 7 to dq 4 : 1v/bit, dq 3 to dq 0 : 100 mv/bit 1dh 0000h v pp min voltage (00h = no v pp pin) 1eh 0000h v pp max voltage (00h =no v pp pin) 1fh 0007h typical timeout per single write 2 n s 20h 0007h typical timeout for min size buffer write 2 n s 21h 000ah typical timeout per individual sector erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms 23h 0001h max timeout for write 2 n times typical 24h 0005h max timeout for buffer write 2 n times typical 25h 0004h max timeout per individual sector erase 2 n times typical 26h 0000h max timeout for full chip erase 2 n times typical 27h 0018h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description 02h : 8/ 16 2ah 2bh 0005h 0000h max number of byte in multi-byte write = 2 n 2ch 0002h number of erase block regions within device (02h = boot) 2dh 2eh 2fh 30h 007fh 0000h 0020h 0000h erase block region 1 information 31h 32h 33h 34h 003eh 0000h 0000h 0001h erase block region 2 information
mbm29pl12lm 10 24 (continued) a 0 to a 6 dq 0 to dq 15 description 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock required 46h 0002h erase suspend (02h = to read & write) 47h 0001h number of sectors in per group 48h 0001h sector temporary unprotection (01h = supported) 49h 0004h sector group protection algorithm 4ah 0000h dual operation (00h = not supported) 4bh 0000h burst mode type (00h = not supported) 4ch 0001h page mode type (01h = 4-word page supported) 4dh 00b5h v acc (acceleration) supply minimum dq 7 to dq 4 : 1v/bit, dq 3 to dq 0 : 100mv/bit 4eh 00c5h v acc (acceleration) supply maximum dq 7 to dq 4 : 1v/bit, dq 3 to dq 0 : 100mv/bit 4fh 00xxh cfi write protect (04h = uniform sectors bottom write protection) 50h 01h program suspend (01h = supported)
mbm29pl12lm 10 25 functional description standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, cmos standby mode is achieved with ce and reset input held at v cc 0.3 v. under this condition the current consumed is less than 5 a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even when ce = "h?. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = ?h? or ?l?) . under this condition the current consumed is less than 5 a max. once the reset pin is set high, the device requires t rh as a wake-up time for output to be valid for read access. during standby mode, the output is in the high impedance state, regardless of oe input. automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of device data. it can be useful in applications such as handy terminal, which requires low power consumption. to activate this mode, the device automatically switch themselves to low power mode when the device addresses remain stable after 30 ns from data valid. it is not necessary to control ce , we , and oe in this mode. the current consumed is typically 1 a (cmos level). since the data are latched during this mode, the data are continuously read out. when the addresses are changed, the mode is automatically canceled and the device read-out the data for changed addresses. autoselect the autoselect mode allows reading out of a binary code and identifies its manufacturer and type.it is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. to activate this mode, the programming equipment must force v id on address pin a 9 . three identifier bytes may then be sequenced from the devices outputs by toggling a 0 . all addresses can be either high or low except a 6 , a 3 ,a 2 ,a 1 and a 0 . see ?mbm29pl12lm user bus operations (word mode : byte = v ih )? and ?mbm29pl12lm user bus operations (byte mode : byte = v il )? in device bus operation. the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in ?mbm29pl12lm standard command definitions? in device bus operation. refer to au- toselect command section. in word mode, a read cycle from address 00h returns the manufacturer?s code (fujitsu = 04h) . a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at addresses of 0eh and 0fh. notice that the above applies to word mode. the addresses and codes differ from those of byte mode. refer to ?sector group protection verify autoselect codes? in device bus operation. read mode the device has two control functions required to obtain data at the outputs. ce is the power control and used for a device selection. oe is the output control and used to gate data to the output pins. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, to input hardware reset or to change ce pin from ?h? or ?l?.
mbm29pl12lm 10 26 page mode read the device is capable of fast read access for random locations within limited address location called page. the page size of the device is 8 bytes / 4 words, within the appropriate page being selected by the higher address bits a 22 to a 2 and the address bits a 1 to a 0 in word mode ( a 1 to a -1 in byte mode) determining the specific word within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the initial page access is equal to the random access (t acc ) and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to the page address access time(t pa c c ). here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode, accesses are obtained by keeping a 20 to a 2 constant and changing a 1 and a 0 in word mode ( a 1 to a -1 in byte mode ) to select the specific word within that page. refer to ?read operation timing diagram? in timing diagram. output disable with the oe input at logic high level (v ih ), output from the devices are disabled. this may cause the output pins to be in a high impedance state. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the device function. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever starts later; while data is latched on the rising edge of we or ce , whichever starts first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the device features hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of 70 sector groups of memory.see ?sector group address table (mbm29pl12lm)? in device bus operation. the user?s side can use the sector group protection using programming equip- ment. the device is shipped with all sector groups that are unprotected. to activate it, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) . the sector group addresses (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , and a 15 ) should be set to the sector to be protected. ?sector group address table (mbm29pl12lm)? in device bus oper- ation defines the sector address for each of the 70 individual sectors, and ?sector group address table (mbm29pl12lm)? in device bus operation defines the sector group address for each of the twenty-four (24) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see ?sector group protection timing diagram? in timing diagram and ?sector group protection algorithm? in flow chart for sector group protection timing diagram and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , and a 15 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical ?1? code at device output dq 0 for a protected sector. otherwise the device will produce ?0? for unprotected sectors. in this mode, the lower order addresses, except for a 0 , a 1 , a 2 , a 3 , and a 6 can be either high or low. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires applying to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses(a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , and a 15 ) are the desired sector group address will produce a logical ?1? at dq 0 for a protected sector group. see ?mbm29pl12lm user bus operations (word mode : byte = v ih ) and ?sector group protection verify autoselect codes? in device bus operation for autoselect codes.
mbm29pl12lm 10 27 temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to ?temporary sector group unprotection timing diagram? in timing diagram and ?temporary sector group unprotection algorithm? in flow chart. hardware reset the devices may be reset by driving the reset pin to v il from v ih . the reset pin has a pulse requirement and has to be kept low (v il ) for at least ?t rp ? in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode ?t ready ? after the reset pin is driven low. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. furthermore, once the reset pin goes high, the devices require an additional ?t rh ? before it will allow read access. write protect (wp ) the write protection function provides a hardware method of protecting certain first 64k bytes / 32k words sector without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the first 64k bytes / 32k words sector independently of whether this sector was protected or unprotected using the method described in ?sector group protection" above. if the system asserts v ih on the wp /acc pin, the device reverts of whether the first 64k bytes / 32k words sectors were last set to be protected to the unprotected status. sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in ?sector protection/ unprotection?. accelerated program operation the device offers accelerated program operation which enables programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 85%. this function is primarily intended to allow high speed programing, so caution is needed as the sector group becomes temporarily unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device is automatically set to fast mode. therefore, the present command and sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from the wp / acc pin while programming. see ?accelerated program timing diagram? in timing diagram. v ccq v ccq determines the mbm29pl12lm voltage output. v ccq facilitates signal exchange within devices that operate in different voltage.
mbm29pl12lm 10 28 command definitions device operations are selected by writing specific address and data sequences into the command register. ?mbm29pl12lm standard command definitions? in device bus operation shows the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover reset commands are functionally equivalent. please note that commands must be asserted to dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the reset operation is initiated by writing the reset command sequence into the command register. the devices remain enabled for reads until the command register contents are altered. the devices will automatically be in the reset state after power-up. in this case, a command sequence is not required in order to read data. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therefore, manufacture and device codes must be accessible while the devices reside in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however applying high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated first by writing two unlock cycles. this is followed by a third write cycle that contains the address and the autoselect command. then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. following the command write, a read cycle from address 00h returns the manufactures?s code (fujitsu = 04h). a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at address of 0eh as well as at 0fh. notice that above applies to word mode. the addresses and codes differ from those of byte mode. refer to ?sector group protection verify autoselect codes? in de- vice bus operation. to terminate the operation, it is necessary to write the reset command into the register. to execute the autoselect command during the operation, reset command must be written before the autoselect command. programming the devices are programmed on a word-by-word basis. programming is a 4 bus cycle operation. there are two ?unlock? write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) starts programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit) or ry/by . the data polling and toggle bit are automatically performed at the memory location being programmed. the programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which the devices return to the read mode and plogram addresses are no longer latched. therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. hence data polling requires the same address which is being programmed. if hardware reset occurs during the programming operation, the data being written is not guaranteed.
mbm29pl12lm 10 29 programming is allowed in any address sequence and across sector boundaries. beware that a data ?0? cannot be programmed back to a ?1?. attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. but a read from reset command will show that the data is still ?0?. only erase operations can convert ?0?s to ?1?s. note that attempting to program a ?1? over a ?0? will result in programming failure. this precaution is the same with fujitsu standard nor devices. ?embedded program tm algorithm? in flow chart illustrates the em- bedded program tm algorithm using typical command strings and bus operations. program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during embedded program operation imme- diately suspends the programming. refer to "erase suspend/resume" for the detail. when the program suspend command is written during a programming process, the chip halts the program operation within 1 s and suspend the status bits.after the program operation has been suspended, the system can read data from any address. normal read timing and command definitions apply. the data at program- suspended address is not valid. after the program resume command (30h) is written, the chip reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see "write operation status" for more information. when issuing program suspend command in 4 s after issuing program command, determine the status of program operation by reading status bit at more 4 s after issuing program resume command. the system also writes the autoselect command sequence in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see "autoselect command sequence" for more information. the system must write the program resume command to exit from the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the chip resumes programming. write buffer programming operations write buffer programming allows the system write to series of 16 words in one programming operation. this results in faster effective word programming time than the standard programming algorithms. the write buffer programming command sequence is initialized by first writing two unlock cycles. this is followed by a third write cycle selecting the sector address in which programming will occur. in forth cycle contains both sector address and unique code for data bus width will be loaded into the page buffer at the sector address in which programming will occur. the system then writes the starting address/data combination. this ?starting address? must be the same sector address used in third and fourth cycles and its lower addresses of a 3 to a 0 should be 0h. all subsequent address must be incremented by 000fh. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) starts programming. upon executing the write buffer programming operations command sequence, the system is not required to provide further controls. the device will automat- ically provide adequate internally generated program pulses and verify the programmed cell margin. dq 7 (data polling), dq 6 (toggle bit), dq 5 (exceeded timing limits), dq 1 (write-to-buffer abort) should be mon- itored to determine the device status during write buffer programming. in addition to these functions, it is also possible to indicate to the host system that write buffer programming operations are either in progress or have been completed by ry/by . see ?hardware sequence flags?. the data polling techniques described in ?data polling algorithm? in flow chart should be used while monitoring the last address location loaded into the write buffer. in addition, it is not neccessary to specify an address in toggle bit techniques described in ?toggle bit algorithm? in flow chart. the automatic pro-
mbm29pl12lm 10 30 graming operation is completed when the data on dq7 is equivalent to the data written to this bit at which time the device returns to the read mode ( see "hardware sequence flags"). the write-buffer programming operation can be suspended/resumed using the standard program suspend/ resume commands. once the write buffer programming is set, the system must then write the ?program buffer to flash? command at the sector address. any other address/data combination will abort the write buffer programming operation and the device will continue busy state. the write buffer programming sequence can be aborted by doing the following : different sector address is asserted. write data other than the ?program buffer to flash" command after the specified number of ?data load? cycles. a ?write-to-buffer-abort reset? command sequence must be written to the device to return to read mode. (see ?mbm29pl12lm standard command definitions? in device bus operation for details on this command sequence.) chip erase chip erase is a 6 bus cycle operation. it begins two ?unlock? write cycles followed by writing the ?set-up? command, and two ?unlock? write cycles followed by the chip erase command which invokes the embedded erase algorithm. the device does not require the user to program the device prior to erase. upon executing the embedded erase algorithm the devices automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the erase operation status by using dq 7 (data polling), dq 6 (toggle bit) and dq 2 (toggle bit ii) or ry/by output signal . the chip erase begins on the rising edge of the last ce or we , whichever happens first from last command sequence and completes when the data on dq 7 is ?1? at which time the device returns to read mode. sector erase sector erase is a 6 bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the sector erase command. multiple sectors may be erased concurrently by writing the same six bus cycle operations. this sequence is followed by writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than erase time-out time(t tow ). otherwise that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can reoccur after the last sector erase command is written. a time-out of ?t tow ? from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the ?t tow ? time- out window the timer is reset (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer). resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete (refer to the write operation status). loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 255). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase using the embedded erase algorithm. when erasing a sector, the remaining unselected sectors remain unaffected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit) or ry/by . the sector erase begins after the ?t tow ? time-out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and completes when the data on dq 7 is ?1? (see write operation status section), at which the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased.
mbm29pl12lm 10 31 erase suspend/resume the erase suspend command allows the user to interrupt sector erase operation and then perform read to a sector not being erased. this command is applicable only during the sector erase operation within the time- out period for sector erase. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the "erase resume" command resumes the erase operation. when the "erase suspend" command is written during the sector erase operation, the device takes maximum of ?t spd ? to suspend the erase operation. when the devices enter the erase-suspended mode, the ry/by output pin will be at high-z and the dq 7 bit will be at logic ?1? and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation is suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. see the section on dq 2 . to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. do not issue program command after entering erase-suspend-read mode. fast mode set/reset the device has fast mode function. it dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming consists of two cycles instead of 4 bus cycles in standard program command. the read operation is also executed after exiting this mode. during the fast mode, do not write any command other than the fast program/fast mode reset command. to exit from this mode, write fast mode reset command into the command register. (refer to the ?embedded program tm algorithm for fast mode? in flow chart.) the v cc active current is required even ce = v ih during fast mode. fast programming during fast mode, the programming can be executed with 2 bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). see ?embedded program tm algorithm for fast mode? in flow chart.
mbm29pl12lm 10 32 extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables protection of the sector group by forcing v id on reset pin and writes a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then the sector group addresses pins (a 22 , a 21 , a 20 , a 19 , a 18 , a 17, a 16 and a 15 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set v il for the other addresses pins is recommended), and write extended sector group protection command (60h). a sector group is typically protected in 250 s. to verify programming of the protection circuitry, the sector group addresses pins (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical ?1? at device output dq 0 will produce for protected sector in the read operation. if the output data is logical ?0?, write the extended sector group protection command (60h) again. to terminate the operation, set reset pin to v ih . (refer to the ?extended sector group protection timing diagram? in timing diagram and ?extended sector group protection algorithm? in flow chart.) query command (cfi : common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward-compatible software sup- port for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is ?0?. refer to the cfi code table. to terminate operation, it is necessary to write the reset command sequence into the register. (see ?common flash memory interface code? in device bus oper- ation.)
mbm29pl12lm 10 33 hiddenrom mode (1) hiddenrom region the hiddenrom (hiddenrom) feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 256 bytes / 128 words in length. after the system writes the hiddenrom entry command sequence, it may read the hiddenrom region by using device addresses a 6 to a 0 (a 22 to a 15 are all ?0?). that is, the device sends only program command that would normally be sent to the address to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the address. if you request fujitsu to program the esn in the device, please contact a fujitsu representative for more information. (2) hiddenrom entry command the device has a hiddenrom region with one time protect function. this area is to enter the security code and to unable the change of the code once set. programming is allowed in this area until it is protected. however, once it gets protected, it is impossible to unprotect. therefore, extreme caution is required. the hiddenrom region is 256 bytes / 128 words. this area is in sa0 . therefore, write the hiddenrom entry command sequence to enter the hiddenrom region. it is called hiddenrom mode when the hiddenrom region appears. sectors other than the block area sa0 can be read during hiddenrom mode. read/program of the hiddenrom region is possible during hiddenrom mode. write the hiddenrom reset command sequence to exit the hid- denrom mode. note that any other commands should not be issued than the hiddenrom program/protection/ reset commands during the hiddenrom mode. when you issue the other commands including the suspend resume capability, send the hiddenrom reset command first to exit the hiddenrom mode and then issue each command. (3) hiddenrom program command to program the data to the hiddenrom region, write the hiddenrom program command sequence during hiddenrom mode. this command is the same as the usual program command, except that it needs to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data pooling, dq 6 toggle bit or ry/by . you should pay attention to the address to be programmed. if an address not in the hiddenrom region is selected, the previous data will be deleted. during the write into the hiddenrom region, the program suspend command issuance is prohibited. (4) hiddenrom protect command there are two methods to protect the hiddenrom region. one is to write the sector group protect setup command (60h) , set the sector address in the hiddenrom region and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence may be used because it is the same as the extension sector group protect in the past, except that it is in the hiddenrom mode and does not apply high voltage to the reset pin. please refer to above mentioned ?extended sector group protection? for details of sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom region and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hiddenrom region, and read. when ?1? appears on dq 0 , the protect setting is completed. ?0? will appear on dq 0 if it is not protected. apply write pulse again. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same as the sector group protect previously men- tioned.
mbm29pl12lm 10 34 take note that other sector groups will be affected if an address other than those for the hiddenrom region is selected for the sector group address. pay close attention that once it is protected, protection cannot be cancelled. write operation status detailed in ?hardware sequence flags? are all the status flags which can determine the status of the device for current mode operation. when checking hardware sequence flags during program operations, it should be checked 4 s after issuing program command. during sector erase, the part provides the status flags automat- ically to the i/o ports. the information on dq 2 is address sensitive. if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows the user to determine which sectors are erasing. once erase suspend is entered address sensitivity still applies. if the address of a non-erasing sector (one available for read) is provided, then stored data can be read from the device. if the address of an erasing sector (one unavailable for read) is applied, the device will output its status bits. hardware sequence flags *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from non-erase suspend sector address will indicate logic ?1? at the dq 2 bit. *3 : dq 1 indicates the write-to-buffer abort status during write-buffer-programming operations. *4 : the data polling algorithm detailed in ?data polling algorithm? in flow chart should be used for write- buffer-programming operations. note that dq 7 during write-buffer-programming indicates the data-bar for dq 7 data for the last loaded write-buffer address location. status dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 * 3 in progress embedded program algorithm dq 7 toggle 0 0 1 0 embedded erase algorithm 0 toggle 0 1 toggle* 1 n/a program suspend mode program-suspend-read (program suspended sector) data data data data data data program-suspend-read (non-program suspended sector) data data data data data data erase suspend mode erase-suspend-read (erase suspended sector) 1 1 0 0 toggle* 1 n/a erase-suspend-read (non-erase suspended sector) data data data data data data erase-suspend-program (non-erase suspended sector) dq 7 toggle 0 0 1* 2 n/a exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 n/a embedded erase algorithm 0 toggle 1 1 n/a n/a erase suspend mode erase-suspend-program (non-erase suspended sector) dq 7 toggle 1 0 n/a n/a write to buffer* 4 busy state dq 7 toggle 0 n/a n/a 0 exceeded timing limits dq 7 toggle 1 n/a n/a 0 abort state n/a toggle 0 n/a n/a 1
mbm29pl12lm 10 35 dq 7 data polling the devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read devices will produce reverse data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. during the embedded erase algorithm, an attempt to read the device will produce a ?0? at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read device will produce a ?1? at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in ?data polling algorithm? in flow chart. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write cycles. data polling must be performed at sector addresses of sectors being erased, not protected sectors. otherwise, the status may become invalid. if a program address falls within a protected sector, data polling on dq7 is active for approximately 1 s, then the device returns to read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 s, then the device returns to read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time, and then that byte?s valid data the next. depending on when the system samples the dq 7 output, it may read the sequence flag or valid data. even if the device completes the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may still be invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algo- rithm, erase suspend mode or sector erase time-out. see ?data polling during embedded algorithm operation timing diagram? in timing diagram for the data polling timing specifications and diagram. dq 6 toggle bit i the device also feature the ?toggle bit i? as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (ce or oe toggling) data from the devices will result in dq 6 toggling between 1 and 0. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write cycles. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write cycles. the toggle bit i is active during the sector time out. in programm operation, if the sector being written to is protected, the toggle bit will toggle for about 1 s and then stop toggling with the data unchanged. in erase, the device will erase all the selected sectors except for the protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. either ce or oe toggling will cause the dq 6 to toggle. see ?toggle bit l timing diagram during embedded algorithm operations? in timing diagram for the toggle bit i timing specifications and diagram.
mbm29pl12lm 10 36 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a ?1?. this is a failure condition indicating that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in ?mbm29pl12lm user bus operations (word mode : byte = v ih )? and ?mbm29pl12lm user bus operations (byte mode : byte = v il )? in device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stop toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a ?1?. note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is ?1? the internally controlled erase cycle has begun. if dq 3 is ?0?, the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see ?hardware sequence flags?. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic ?1? at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also ?hardware sequence flags? and ?dq 2 vs. dq 6 ? in timing dia- gram. furthermore, dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector.
mbm29pl12lm 10 37 reading toggle bits dq 6 / dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to ?toggle bit algorithm? in flow chart.) toggle bit status *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from the non-erase suspend sector address will indicate logic ?1? at the dq 2 bit. dq 1 write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a "1". the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data. see "write buffer programming operations" section for more details. ry/by ready/busy the device provides a ry/by open-drain output pin to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high impedance, the device is ready to accept any write or erase operation. if the device is placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull-up resister. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a ready condition during the reset is v il . see ?ry/by timing diagram during program/erase operation timing diagram? and ?reset timing diagram ( during embedded algorithms )? in ? timing diagram? for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle *1 erase-suspend-read (erase-suspended sector) 11toggle *1 erase-suspend-program dq 7 toggle 1 *2
mbm29pl12lm 10 38 word/byte configuration byte pin selects the byte (8-bit) mode or word (16-bit) mode for the device. when this pin is driven high, the device operates in the word (16-bit) mode. data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the device operates in byte (8-bit) mode. in this mode, dq 15 /a -1 pin becomes the lowest address bit, and dq 14 to dq 8 bits are high-z. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically reset the internal state machine in read mode. also, with its command register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. (1) low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the user?s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko . if embedded erase algorithm is interrupted, the intervened erasing sector(s) is(are) not valid. (2) write pulse ?glitch? protection noise pulses of less than 3 s (typical) on oe , ce , or we will not initiate a write cycle. (3) logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be low while oe is high. (4) power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically set to read mode on power-up. (5) sector protection device is able to protect each sector group to store and protect data in the user side. protection circuit voids both write and erase commands that are addressed to protected sectors. any commands to write or erase addressed to protected sector are ignored . see ?sector group protection? in functional description.
mbm29pl12lm 10 39 absolute maximum ratings *1 : voltage is defined on the basis of vss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to ?0.2 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns *3 : minimum dc input voltage is ?0.5v. during voltage transitions, these pins may undershoot v ss to ?0.2 v for periods of up to 20 ns.voltage difference between input and supply voltage ( v in ?v cc ) dose not exceed to +9.0 v. maximum dc input voltage is +12.5 v which may overshoot to +14.0 v for periods of up to 20 ns . warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating ranges * 1 *1 : operating ranges define those limits between which the functionality of the device is guaranteed. *2 : voltage is defined on the basis of v ss = gnd = 0v. *3 : see if v cc and v ccq are of the same value. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg ?55 +125 c ambient temperature with power applied t a ?20 +85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in , v out ?0.5 v cc +0.5 v power supply voltage * 1 v cc ?0.5 +4.0 v a 9 , oe , and reset * 1, * 3 v in ?0.5 +12.5 v wp /acc * 1, * 3 v acc ?0.5 +12.5 v parameter symbol value unit min max ambient temperature 10 t a ?20 +85 c v cc supply voltage * 2, * 3 v cc +3.0 +3.6 v v ccq supply voltage * 2, * 3 v ccq v cc v
mbm29pl12lm 10 40 maximum overshoot/maximum undershoot maximum undershoot waveform +0.6 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns maximum overshoot waveform 1 0.7 v cc v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc +0.5 v +12.5 v 20 ns +14.0 v 20 ns 20 ns note: this waveform is applied for a 9 , oe , reset, and wp /acc.
mbm29pl12lm 10 41 electrical characteristics 1. dc characteristics parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max wp /acc pin ?2.0 ? +2.0 a others ?1.0 ? +1.0 output leakage current i lo v out = v ss to v cc , v cc = v cc max ?1.0 ? +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ??35a v cc active current (read ) * 1, * 2 i cc1 ce = v il , oe = v ih , f = 5 mhz word ? 15 25 ma byte ? 15 25 ce = v il , oe = v ih , f = 10 mhz word ? 35 50 byte ? 35 50 v cc active current (intra-page read ) * 2 i cc2 ce = v il , oe = v ih , t prc = 25ns, 4-word ?1020ma v cc active current (program / erase) * 2, * 3 i cc3 ce = v il , oe = v ih ?5060ma v cc standby current * 2 i cc4 ce = v cc 0.3 v, reset = v cc 0.3 v, oe = v ih , wp /acc = v cc 0.3 v ?15a v cc reset current * 2 i cc5 reset = v cc 0.3 v, wp /acc = v cc 0.3 v ?15a v cc automatic sleep current * 4 i cc6 ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3v or v ss 0.3v, wp /acc = v cc 0.3 v ?15a v cc active current (erase-suspend-program) * 2 i cc7 ce = v il , oe = v ih ?5060ma acc accelerated program current i acc ce = v il , oe = v ih , vcc = vcc max, wp /acc =v acc max wp /acc pin ? ? 45 ma vcc pin ? ? 60 input low level v il ? ?0.5 ? 0.6 v input high level v ih ?0.7 v cc ?v cc + 0.3 v voltage for wp /acc sector protection/unprotection and program acceleration v acc v cc = 3.0 v to 3.6 v 11.5 12.0 12.5 v voltage for autoselect, and temporary sector unprotected v id v cc = 3.0 v to 3.6 v 11.5 12.0 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min ? ? 0.45 v output high voltage level v oh i oh = ?2.0 ma, v cc = v cc min 0.85 v ccq ??v low v cc lock-out voltage v lko ?2.3?2.5v
mbm29pl12lm 10 42 *1 : the l cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc peaks when both v cc and v ccq are at their max. *3 : i cc active while embedded erase or embedded program or write buffer programming is in progress. *4 : automatic sleep mode enables the low power mode when address remain stable for t acc + 30 ns.
mbm29pl12lm 10 43 2. ac characteristics ? read only operations characteristics * : test conditions : output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc timing measurement reference level input : v cc / 2 output : v cc / 2 parameter symbols condition value* unit 10 jedec standard min max read cycle time t avav t rc ? 100 ? ns address to output delay t avqv t acc ce = v il , oe = v il ? 100 ns chip enable to output delay t elqv t ce oe = v il ? 100 ns page read cycle time ? t prc ?25 ? ns page address to output delay ? t pacc ce = v il , oe = v il ? 30 ns output enable to output delay t glqv t oe ? ? 30 ns chip enable to output high-z t ehqz t df ? ? 25 ns output enable hold time read ?t oeh ?0 ? ns toggle and data polling ? 10 ? ns output enable to output high-z t ghqz t df ? ? 25 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ?0 ? ns reset pin low to read mode ? t ready ? ? 20 s test conditions c l 3.3 v diode = 1n3064 or equivalent 2.7 k ? device under test diode = 1n3064 or equivalent 6.2 k ? ? output load circuit
mbm29pl12lm 10 44 ? write (erase/program) operations (continued) parameter symbol value unit 10 jedec standard min typ max write cycle time t avav t wc 100 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling ?t aso 15 ?? ns address hold time t wlax t ah 45 ?? ns address hold time from ce or oe high during toggle bit polling ?t aht 0 ?? ns data setup time t dvwh t ds 45 ?? ns data hold time t whdx t dh 0 ?? ns output enable setup time ? t oes 0 ?? ns ce high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write (oe high to we low) t ghwl t ghwl 0 ?? ns read recover time before write (oe high to ce low) t ghel t ghel 0 ?? ns ce setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns ce pulse width t eleh t cp 35 ?? ns write pulse width t wlwh t wp 35 ?? ns ce pulse width high t ehel t cph 25 ?? ns write pulse width high t whwl t wph 30 ?? ns effective page programming time (write buffer programming) per word t whwh1 t whwh1 ? 23.5 ? s programming time word ? 100 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1.0 ? s v cc setup time ? t vcs 50 ?? s recovery time from ry/by ?t pb 0 ?? ns erase/program valid to ry/by delay ? t busy ?? 90 ns rise time to v id * 2 ?t vidr 500 ?? ns rise time to v acc * 3 ?t vaccr 500 ?? ns voltage transition time * 2 ?t vlht 4 ?? s
mbm29pl12lm 10 45 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector group protection operation. *3 : this timing is for accelerated program operation. parameter symbol value unit 10 jedec standard min typ max write pulse width * 2 ?t wpp 100 ?? s oe setup time to we active * 2 ?t oesp 4 ?? s ce setup time to we active * 2 ?t csp 4 ?? s reset pulse width ? t rp 500 ?? ns reset high time before read ? t rh 100 ?? ns delay time from embedded output enable ?t eoe ?? 100 ns erase time-out time ? t tow 50 ?? s erase suspend transition time ? t spd ?? 20 s
mbm29pl12lm 10 46 erase and programming performance tsop (1) pin capacitance notes : ? test conditions t a = + 25c, f = 1.0 mhz ? dq 15 /a- 1 pin capacitance is stipulated by output capacitance. fbga pin capacitance notes : ? test conditions t a = + 25c, f = 1.0 mhz ? dq 15 /a- 1 pin capacitance is stipulated by output capacitance. parameter limits unit remarks min typ max sector erase time ? 1 15 s excludes programming time prior to erasure programming time ? 100 3000 s excludes system-level overhead effective page programming time (write buffer programming) ? 23.5 ? s chip programming time ? ? 1200 s absolute maximum programming time (16 words) ??6ms non programming within the same page erase/program cycle 100,000 ? ? cycle ? parameter symbol test setup value unit typ max input capacitance c in v in = 0 8 10 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf reset pin and wp /acc pin capacitance c in3 v in = 0 20 25 pf parameter symbol test setup value unit typ max input capacitance c in v in = 0 8 10 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf reset pin and wp /acc pin capacitance c in3 v in = 0 15 20 pf
mbm29pl12lm 10 47 timing diagram key to switching waveforms read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h ?h? or ?l? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?off? state we oe ce t acc t df t ce t oh t oe data t rc address address stable high-z output valid high-z t oeh
mbm29pl12lm 10 48 reset t acc t oh data t rc address address stable high-z output valid t rh ce t rp t rh t ce data a 1 to a 0 (a -1 ) a 22 to a 2 ce oe we aa ab ac t rc t acc t ce t oe t oh t oh t oh t df t pacc t pacc t oeh t prc da db dc address valid high-z page read operation timing diagram hardware reset/read operation timing diagram
mbm29pl12lm 10 49 notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates the last two bus cycles out of four bus cycle sequence. t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df alternate we controlled program operation timing diagram
mbm29pl12lm 10 50 t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates the last two bus cycles out of four bus cycle sequence. alternate ce controlled program operation timing diagram
mbm29pl12lm 10 51 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase ry/by t busy sa* 30h t tow * : sa is the sector address for sector erase. address = 555h (word), aaah (byte) for chip erase. chip/sector erase operation timing diagram
mbm29pl12lm 10 52 address data ce we xxxh t wc t cs t ch t wp t ds b0h ry/by t spd erase suspend operation timing diagram
mbm29pl12lm 10 53 t oeh t ch t oe t ce t df t eoe t busy t whwh1 or 2 ce dq 7 ry/by dq 6 to dq 0 dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we address high-z high-z data data * va 4 s * : dq 7 = valid data (the device has completed the embedded operation.) note : when checking hardware sequence flags during program operations, it should be checked 4 s after issuing program command. data polling during embedded algorit hm operation timing diagram
mbm29pl12lm 10 54 * : dq 6 stops toggling (the device has completed the embedded operation). note : when checking hardware sequence flags during program operations, it should be checked 4 s after issuing program command. t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh 4 s t oeph t aht t aht t aso t as t ceph toggle bit timing diagram during embedded algorithm operations * : dq 2 is read from the erase-suspended sector. dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce dq 2 vs. dq 6
mbm29pl12lm 10 55 rising edge of the last we signal ce ry/by we t busy entire programming or erase operations ry/by timing diagram during program/erase operation timing diagram reset t ready ce , oe t rh t rp reset timing diagram (not during embedded algorithms)
mbm29pl12lm 10 56 t rp reset t ready ry/by we t rb reset timing diagram (during embedded algorithms)
mbm29pl12lm 10 57 t vlht sgax a 22 , a 21 , a 19 , a 18 , a 17 , a 16 , a 15 sgay a 6 , a 3 , a 2 , a 0 a 9 v ih t vlht oe v ih t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs v id v id sgax : sector group address to be protected sgay : next sector group address to be protected sector group protection timing diagram
mbm29pl12lm 10 58 reset ce we ry/by t vlht program or erase command sequence t vlht t vidr v id unprotection period t vcs t vlht v cc v ss , v il or v ih temporary sector group unprotection timing diagram
mbm29pl12lm 10 59 sgax: sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 s (min) sgay reset oe we ce data a 1 v cc a 6 , a 3 , a 2 , a 0 add sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe extended sector group protection timing diagram
mbm29pl12lm 10 60 v cc ce we t vlht program command sequence t vlht t vcs t vaccr v acc t vlht acceleration period acc accelerated program timing diagram
mbm29pl12lm 10 61 flow chart 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress embedded algorithms note : the sequence is applied for word ( 16 ) mode. the addresses differ from byte ( 8 ) mode. embedded program tm algorithm
mbm29pl12lm 10 62 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional. embedded algorithms note : the sequence is applied for word ( 16 ) mode. the addresses differ from byte ( 8 ) mode. embedded erase tm algorithm
mbm29pl12lm 10 63 dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass wait 4 s after issuing program command * : dq 7 is rechecked even if dq 5 = ?1? because dq 7 may change simultaneously with dq 5 . va = valid address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase operation data polling algorithm
mbm29pl12lm 10 64 *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to ?1?. dq 6 = toggle dq 5 = 1? read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" start no no yes yes *1 *1, *2 ? no yes program/erase operation not complete.write reset command program/erase operation complete dq 6 = toggle ? read dq 7 to dq 0 addr. = "h" or "l" *1, *2 *1 wait 4 s after issuing program command toggle bit algorithm
mbm29pl12lm 10 65 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? increment plscnt read from sector group addr. = sga, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 ) oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 s we = v ih , ce = oe = v il (a 9 should remain v id ) () * : a -1 is v il in byte ( 8 ) mode. sector group protection algorithm
mbm29pl12lm 10 66 reset = v id *1 perform erase or program operations reset = v ih start temporary sector group unprotection completed *2 *1 : all protected sector groups are unprotected. *2 : all previously protected sector groups are protected. temporary sector group unprotection algorithm
mbm29pl12lm 10 67 to protect sector group yes no no plscnt = 1 protection other sector start sector group protection extended sector group completed remove v id from reset write reset command reset = v id wait to 4 s protection entry? to setup sector group protection write xxxh/60h write 60h to sector address (a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) time out 250 s to verify sector group protection write 40h to sector address (a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) data = 01h? group ? device is operating in temporary sector group read from sector group ( a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) increment plscnt no yes yes unprotection mode address setup next sector group address no yes plscnt = 25? device failed remove v id from reset write reset command extended sector group protection algorithm
mbm29pl12lm 10 68 fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify data? no program address/program data data polling last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode notes : ? the sequence is applied for word ( 16 ) mode. ? the addresses differ from byte ( 8 ) mode. embedded program tm algorithm for fast mode
mbm29pl12lm 10 69 ordering information part no. package access time remarks MBM29PL12LM10PCN 56-pin, plastic tsop (1) (fpt-56p-m01) (normal bend) 100 ns mbm29pl12lm10pbt 80-ball,plastic fbga (bga-80p-m02) 100 ns mbm29pl12lm device number/description 128 mega-bit (16m 8/8m 16) mirrorflash with page mode, boot sector 3.0 v-only read, program, and erase package type pcn = 56-pin thin small outline package (tsop(1)) standard pinout pbt = 80-ball fine pitch ball grid array package (fbga) 10 pcn speed option 10 = 100 ns access time
mbm29pl12lm 10 70 package dimensions (continued) 56-pin plastic tsop(1) (fpt-56p-m01) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note : the values in parentheses are reference values. c 2002 fujitsu limited f56001s-c-4-5 18.400.10(.724.004) 20.000.20(.787.008) 14.000.10 m 0.10(.004) 0.100.05 (.004.002) 1 28 56 29 0.08(.003) (.551.004) (stand off) lead no. details of "a" part 0.600.15 (.024.006) 0?~8? .007.001 0.170.03 0.220.05 (.009.002) (mounting height) index "a" .043 ?.002 +.004 ?0.05 +0.10 1.10 0.50(.020) 0.25(.010) * 1 * 2
mbm29pl12lm 10 71 (continued) 80-ball, plastic fbga (bga-80p-m02) dimensions in mm (inches). note : the values in parentheses are reference values. c 2003 fujitsu limited b80002s-c-1-1 13.00 0.10(.512 .004) 10.00 0.10 (.394 .004) index area 0.38 0.10 (.015 .004) (stand off) a b c d e f g h j k l m 1 2 3 4 5 6 7 8 (80- ? .018 .002) 80- ? 0.45 0.05 0.08(.003) m s a b b ref 0.80(.031) ref 0.40(.016) a s s 0.10(.004) (index area) .043 ?.005 +.005 ?0.13 +0.12 1.08 (mounting height)
mbm29pl12lm 10 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0405 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant noninfringement of any thirdpartys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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